1. Field of the Invention
The present invention relates to integrated circuit manufacturing, and relates particularly to structures and methods for reducing the capacitance of conductor members in integrated circuits to produce an increase in switching speed and a reduction in cross-talk between the conductor members.
2. Description of the Prior Art
The continuing increases in component density and switching speed in current integrated circuits leads to a continuing need for improvements in process developments and structures utilized in the manufacture of these circuits.
As is well known, the response speed of an integrated circuit is determined by its time constant RC, where R is the resistance of the conductors in the circuit and C is the distributed capacitance between the conductors. The resistance R is determined by the resistivity of the conductors and can be decreased by increasing the physical size of the conductors. However, with the continuing emphasis on increasing miniaturization of integrated circuit components, there is a practical limit to the increases in the physical size of the conductors which can be employed and still remain commercially attractive.
The distributed capacitance between conductors is a function of the dielectric constant of the medium between the conductors. The dielectric constant of a vacuum is 1.0 and that of air is near 1.0, while the dielectric constant of silicon dioxide, a material which is commonly deposited between conductors in current integrated circuit manufacturing, is near 3.9. This relatively high dielectric constant for silicon dioxide and similar materials used for that purpose results in an undesirably high value of capacitance between the conductors, with a consequent increase in the circuit time constant and response time.
The following references discuss approaches which have been proposed in the prior art to reduce the dielectric constant between conductors in integrated circuit structures in order to increase the response speed.
U.S. Pat. No. 5,310,700, Lien et al, describes a fabrication technique for reducing the capacitance between spaced conductor members in a semiconductor structure by utilizing chemical vapor deposition (CVD) of an oxide film to create voids or air gaps between the conductor members in the oxide film surrounding the conductor members. In one embodiment, layers of insulating or conductive material are formed on top of the conductor members and extend over the edges of the conductor members to facilitate the formation of the air gaps therebetween during subsequent etching of the deposited oxide film.
A publication entitled Use of Air Gap Structures To Lower Intralevel Capacitance, Fleming et al, DUMIC Conference, February 1997, page 139, describes a process which creates low dielectric air gaps between conductors by first coating the structure using a CVD process with silicon dioxide having poor step coverage. The open areas and reentrant features in the structure resulting from this step are then filled with a material having a lower dielectric constant than silicon dioxide, such as hydrogen silsesquioxane (HSQ). However, this process does not provide for changing the shape or location of the air gaps after their initial formation, and the air gap formation provided thereby is determined solely by the step coverage of the CVD oxide and the metal spacings. In addition, the use of SOG in that reference increases the process complexity and may result in some process integration difficulties.
U.S. Pat. No. 5,278,103, Mallon et al, describes a method for producing controllable voids in doped glass dielectric films between conductors by flowing a layer of doped glass having voids therein to a thickness having a predetermined ratio with the size of the spacing between the conductors. This doped glass layer is reflowed to smooth the surface thereof without removing the desired voids therein. One or more additional doped glass layers may be applied to achieve the desired glass thickness. However, this technique can be applied only to conductors which can withstand the reflow temperature of doped glass, and is not applicable to metal layers with melting points lower than the reflow temperature of doped glass, such as aluminum alloys.